The 386 microcode sequencer has a one-cycle pipeline delay: when a jump or RNI (run next instruction) is decoded, the micro-instruction immediately after it has already been fetched and will execute before the jump takes effect. This "delay slot" is a basic property of the sequencer, and the microcode is written to fill it with useful work rather than waste a cycle on a bubble. The examples in the PTSAV section above show this: at 582/5AE, the micro-instruction after LCALL executes before the subroutine begins.
The spectrumPutting it all together, the landscape spans from fast and weak isolation to slower and highly secure isolation.
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The solution is trap-and-emulate, the same principle later generalized in hardware virtualization extensions. V86 mode adds a special rule: since V86 tasks always run at CPL=3, if the OS sets IOPL